----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:24:26 10/05/2013 
-- Design Name: 
-- Module Name:    add_sub_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- does addition or subtraction depending on subControl
-- subControl = '1' then subtract else add
entity add_sub_32 is
    Port ( subControl : in STD_LOGIC;
			  a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
			  result : out  STD_LOGIC_VECTOR (31 downto 0);
           carryOut : out  STD_LOGIC);
end add_sub_32;

architecture Behavioral of add_sub_32 is
	signal addResult, subResult : STD_LOGIC_VECTOR(32 downto 0);
begin
	addResult <= ('0' & a) + ('0' & b);
	subResult <= ('0' & a) + ('0' & not(b)) + 1;
	result <= 	addResult(31 downto 0) when subControl = '0' else
					subResult(31 downto 0);
	carryOut <= addResult(32) when subControl = '0' else
					NOT(subResult(32));
end Behavioral;

